Electric power converter

ABSTRACT

By reduction in loss and noise of a three-phase reactor on the AC side of an electric power converter, compactness and reduction in weight of the reactor are realized, and countermeasures for heat and noise are reduced, and a specific frequency component is reduced, thus cost reduction and conversion efficiency are improved, and carriers of a controller are prepared in correspondence to the phases of the electric power converter, and moreover a phase difference of each carrier is set properly.

FIELD OF THE INVENTION

The present invention relates to an electric power converter.

BACKGROUND OF THE INVENTION

In the electric power converter, for example, as shown in FIG. 1 of Japanese Patent Laid-open No. Hei 3 (1991)-218270, to remove high-frequency components generated in an AC line and a DC line, a capacitor is connected between the AC line and the DC line. The converter compares signal waves of respective phases having a phase difference from one carrier common to the respective phases, gives positive logic and negative logic high frequency pulses, which are output of comparators, to switching devices to control the PWM.

When a function for removing the high-frequency components generated in the AC line and DC line is provided, the following advantages can be obtained.

(1) Without insulating the AC line and electric power converter by a transformer, a leakage current Ir can be reduced.

(2) A high-frequency current leaking from the electric power converter is reduced, so that an EMI countermeasure can be taken.

SUMMARY OF THE INVENTION

However, there is a circuit through which an excessive high-frequency current I₀ flows, so that loss and noise of a reactor installed between the AC line and the DC line are increased.

An object of the present invention is to reduce the high-frequency current I₀, reduce the loss and noise of the reactor, and furthermore realize compactness, cost reduction, and improvement of the conversion efficiency of the electric power converter by reduction in the loss and noise.

The present invention installs a carrier source for each phase and gives a phase difference to a carrier of each phase.

Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic view of a three-phase three-wire inverter circuit,

FIG. 2 is a drawing showing the phase relationship of the signal wave and carrier in the circuit shown in FIG. 1,

FIG. 3 is a schematic view of a three-phase four-wire inverter circuit when two DC power sources are used, and

FIG. 4 is a schematic view of a three-phase four-wire inverter circuit when one DC power source is used.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a circuit diagram showing the electric power converter of an embodiment of the present invention, which is composed of a main circuit 12, a load system 6, and PMW controller 13. The main circuit 12 is structured so as to connect 6 switching devices T1, T2, T3, T4, T5, and T6 and diodes D1, D2, D3, D4, D5, and D6 connected respectively to the switching devices T1 to T6 in parallel as a three-phase bridge. To the DC side of the three-phase bridge circuit, DC power supplies 9A and 9B connected in series are connected.

The switching devices T1 to T6 of the main circuit 12 are driven by an on-off control signal for PWM (pulse width modulation) control given from the PWM controller 13 and function as a voltage source PWM converter.

The AC side of the main circuit 12 is connected to the load system 6 via the AC lines. The DC side of the main circuit 12 is connected to the AC side via the line N. Into the phases of the AC lines, reactors 4 are respectively inserted and between the AC lines of the reactors 4 on the load system side and the line N, capacitors 5 u, 5 v, and 5 w are connected. In this embodiment, the line N is connected to the middle point of the DC power supplies 9A and 9B.

A high frequency filter is formed by these reactors 4 and the capacitors 5 u, 5 v, and 5 w. In the PWM controller 13, according to the relative sizes of carriers 1 u, 1 v, and 1 w and signal waves 2 u, 2 v, and 2 w, comparators 3 u, 3 v, and 3 w output an ON signal or an OFF signal.

The output of the comparators 3 u, 3 v, and 3 w is supplied to the respective switching devices T1 to T6 directly or via NOT circuits 14 u, 14 v, and 14 w. The frequency of the carriers 1 u, 1 v, and 1 w is, for example, about 7 kHz. Between the load system 6 and the earth, a parasitic capacitor 7 is formed and between the electric power converter and the earth, a parasitic capacitor 8 is formed.

The output of the comparators 3 u, 3 v, and 3 w is transferred to the switching devices T1 to T6 in a three-phase bridge circuit 11. Further, the carriers 1 u, 1 v, and 1 w are given an optimal phase difference. The value of a phase difference γ of the carrier of each phase is decided by Formulas (8) and (9) as indicated below. Further, even if the phase difference of the carrier of each phase is set to the values other than those of Formulas (8) and (9), an effect can be obtained.

When a signal wave is set to a sine wave and a carrier is set to a triangle wave, the frequency component of each phase is given by Formulas (1) and (2) indicated below. In addition, the relation between the signal wave and carrier is shown in FIG. 2. (Reference: “Semiconductor Power Conversion Circuit, Electric Society, Semiconductor Electric Power Conversion System Investigation Committee”, Electric Society, pp. 116-117; The same point of view as the reference can be used.)

When n=1, 3, 5, $\begin{matrix} \left\lbrack {{Formula}\quad 1} \right\rbrack & \quad \\ {\left( {- 1} \right)^{{({n + 1})}/2}{\left( \frac{4}{n\quad\pi} \right)\left\lbrack {{J_{k}\left( \frac{{an}\quad\pi}{2} \right)}\left\{ {{\cos\left( {{\left( {{k\quad\omega_{0}} + {n\quad\omega_{S}}} \right)t} + {k\quad\phi}} \right)} + {\cos\left( {{\left( {{k\quad\omega_{0}} - {n\quad\omega_{S}}} \right)t} + {k\quad\phi}} \right)}} \right\}} \right\rbrack}} & (1) \end{matrix}$

It is assumed that k=2λ and λ=0, 1, 2, 3, . . . .

When n=2, 4, 6, . . . $\begin{matrix} \left\lbrack {{Formula}\quad 2} \right\rbrack & \quad \\ {\left( {- 1} \right)^{n/2}\quad{\left( \frac{4}{n\quad\pi} \right)\left\lbrack \quad{{J_{k}\left( \frac{{an}\quad\pi}{2} \right)}\quad\left\{ {{\sin\left( {{\left( {{k\quad\omega_{0}} + {n\quad\omega_{S}}} \right)\quad t} + {k\quad\phi}} \right)} + {\sin\left( {{\left( {{k\quad\omega_{0}} - {n\quad\omega_{S}}} \right)\quad t} + {k\quad\phi}} \right)}} \right\}} \right\rbrack}} & (2) \end{matrix}$

It is assumed that λ=2λ+1 and λ=0, 1, 2, 3, . . . .

n: degree of harmonics of carrier, k: degree of harmonics concerning signal wave, a: modification factor, ω₀: angular frequency of signal wave, ω_(s): fundamental angular frequency of carrier wave, φ: phase of signal wave, Jk(x): Bessel function of the first kind)

In Formulas (1) and (2), the amplitude does not depend at all on the phase difference between the signal wave and the carrier. Therefore, only the phases in the sin and cos may be considered. Furthermore, in Formulas (1) and (2), in consideration of only the phase of the carrier, Formulas (3) to (5) indicated below are substituted for Formulas (1) and (2).

[Formula 3] t=t′+δ  (3) φ=−ω₀δ+θ  (4) γ=ω_(s)δ  (5)

δ: time difference of carrier, t′: time, θ: phase difference of signal wave, γ: phase difference of carrier

The inside of each of the items of cos and sin of Formulas (1) and (2) for which Formulas (3) to (5) indicated below are substituted is as indicated in Formula (6).

[Formula 4] (kω ₀ ±nω _(s))t+kθ±nγ  (6)

In Formula (6), the part different in each phase is only the item of Formula (7). kθ±nγ  (7)

Furthermore, in consideration of only n=1 and k=0 which are main components of the harmonics of I₀, only γ remains. To negate the main components of the harmonics of I₀ by the phase differenceγ of the carrier of each phase, when the phase difference γ calculated by Formula (8) is set in each phase, I₀ can be made smaller. $\begin{matrix} \left\lbrack {{Formula}\quad 5} \right\rbrack & \quad \\ {\gamma = \frac{2\pi\quad q}{p}} & (8) \end{matrix}$

p: phase of electric power converter

q: integer (for example, when p=3, q= . . . , −7, −5, −2, −1, +1, +2, +4, +5, +7, . . . ) meeting p≠0 in mode q

Further, in I₀, to negate the frequency components other than n=1 and k=0, Formula (9) must be satisfied. $\begin{matrix} \left\lbrack {{Formula}\quad 6} \right\rbrack & \quad \\ {{{k\quad\theta} \pm {n\quad\gamma}} = \frac{2\quad\pi\quad q}{p}} & (9) \end{matrix}$

The main circuit 12, according to the output of the comparators 3 u, 3 v, and 3 w in the PWM controller 13, turns on or off the switching devices T1 to T6. The output of the DC power sources 9A and 9B, via the switching devices T1 to T6 and the diodes D1 to D6, is transferred to the three-phase AC reactor 4 as pulse-shaped power including the high-frequency component.

The capacitors 5 u, 5 v, and 5 w connected to the three-phase AC reactor 4 return the high-frequency current flowing through the three-phase AC reactor 4 to the DC power sources 9A and 9B by the neutral line N. Furthermore, among the current flowing through the three-phase AC reactor 4, the smooth currents in which the high-frequency current is removed by the capacitors 5 u, 5 v, and 5 w are transferred to the load system 6.

In FIG. 1, when the phase difference γ is set to 0 and in the same way as with FIG. 2, only n=1 and k=0, which are the main components of high frequency of I₀, are considered, I₀ is decided as shown in Formula (10). $\begin{matrix} \left\lbrack {{Formula}\quad 7} \right\rbrack & \quad \\ {\frac{3{{Ed}/2}}{\omega_{S}L}\left( {- \frac{4}{\pi}} \right){J_{0}\left( \frac{a\quad\pi}{2} \right)}\left\{ {2{\cos\left( {\omega_{S}t} \right)}} \right\}} & (10) \end{matrix}$

L: inductance per phase of three-phase reactor 4, Ed/2: voltage of DC power supplies 9A and 9B

Further, the components of I₀ concerning n=1 and k=2 are negated in each phase, so that they are 0. When γ=2π/3 is applied from Formula (8), Formula (10) becomes 0. However, n=1 and k=2 which are negated mutually do not meet Formula (9), so that Formula (11) is obtained and they will not negate mutually. Further, in Formula (11), ω_(s)□ω₀ is set, so that the impedance of the three-phase reactor 4 per phase is approximate to ω_(s)L. $\begin{matrix} \left\lbrack {{Formula}\quad 8} \right\rbrack & \quad \\ {\frac{3{{Ed}/2}}{\omega_{S}L}{\left( {- \frac{4}{\pi}} \right)\left\lbrack {{J_{2}\left( \frac{a\quad\pi}{2} \right)}\left\{ {{\cos\left( {\left( {{2\omega_{0}} + \omega_{S}} \right)t} \right)} + {\cos\left( {\left( {{2\omega_{0}} - \omega_{S}} \right)t} \right)}} \right\}} \right\rbrack}} & (11) \end{matrix}$

In 0≦a≦1, the magnitude relations of the amplitude of Formulas (10) and (11) are as indicated in Formula (12), so that I₀ can be reduced. $\begin{matrix} \left\lbrack {{Formula}\quad 9} \right\rbrack & \quad \\ {{\frac{3{{Ed}/2}}{\omega_{S}L}\left( {- \frac{4}{\pi}} \right){J_{0}\left( \frac{a\quad\pi}{2} \right)} \times 2} > {\frac{3{{Ed}/2}}{\left( {\omega_{0} + \omega_{S}} \right)L}\left( {- \frac{4}{\pi}} \right){J_{2}\left( \frac{a\quad\pi}{2} \right)} \times \sqrt{2}}} & (12) \end{matrix}$

The three-phase three-wire inverter circuit is described above. Next, an embodiment when the present invention is applied to the three-phase four-wire inverter circuit shown in FIG. 3 will be described. The difference between FIGS. 1 and 3 is that in FIG. 1, the neutral line N is not connected to the load system 6, while in FIG. 3, the neutral line N is connected to the load system 6. In FIG. 3, the different part from FIG. 1 will be explained mainly, though the main realization is the same as that shown in FIG. 1. In FIG. 3, the neutral phase N is formed using the two DC power supplies 9A and 9B. Depending on the conditions of the power sources, only one power source may require the three-phase four-wire inverter circuit. When only one power source requires the three-phase four-wire inverter circuit, the capacitors 5 p and 5 n shown in FIG. 4 form the neutral phase N. However, when a large common-mode current flows, the voltages of the capacitors 5 p and 5 n are unbalanced and a problem arises that the output voltage waveform is distorted. Therefore, in FIG. 4, one arm is added (switching devices T7, T8, D7, and D8 are added) and the balance of the voltages of the capacitors 5 p and 5 n is controlled. The differences between FIGS. 3 and 4 are as indicated in (1) to (4) described below.

(1) Addition of one arm (addition of switching devices T7, T8, D7, and D8)

(2) Addition of controller for one arm (addition of carrier 1 n, etc.)

(3) Four-phase reactor 15 (three-phase reactor 4 shown in FIG. 3)

(4) Addition of capacitors 5 p and 5 n

When the present invention is applied to the circuit shown in FIG. 4, by selection of the phase differences γ1 to γ3 of the carrier so that the common-mode current of high frequency flowing through the four-phase reactor 15 shown in FIG. 4 is minimized, the loss and noise of the reactor can be reduced.

By change of structure only of the controller, the loss and noise of the reactor can be reduced, thus compactness and reduction in weight of the reactor can be realized and countermeasures for heat and noise can be reduced. Furthermore, a specific frequency component can be reduced, so that an EMI countermeasure can be taken. Therefore, cost reduction and improvement of the conversion efficiency can be provided.

The foregoing disclosure has been set forth merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof. 

1. A method of converting electric power between AC power and DC power, comprising the steps: providing a switching device between an AC circuit and at least one DC line of a DC circuit; providing a reactor having one side connected to said switching device and another side connected to at least one phase of said AC circuit and said another side being further connected to any one of said at least one DC line by at least one capacitor; providing a plurality of carrier waves having a phase difference among said plurality of carrier waves; generating a signal as a function of characteristics said plurality of carrier waves; and converting DC power on said at least one DC line to AC power or converting AC power on said AC circuit to DC power to thereby provide improved conversion efficiency by reduction in energy loss and a reduction in noise from the reactor.
 2. The method according to claim 1 wherein said at least one DC lines includes two DC lines and said capacitor is connected between said two DC lines.
 3. The method according to claim 1 wherein said AC circuit has three lines each of said lines being connected by a respective capacitor to said at least one DC line.
 4. The method according to claim 1 wherein said switching device functions as a Pulse Width Modulation converter.
 5. An apparatus for converting electric power between AC power and DC power, comprising: a switching device connected between an AC circuit and at least one DC line of a DC circuit; a reactor having one side connected to said switching device and another side connected to at least one phase of said AC circuit and said another side being further connected to any one of said at least one DC line by at least one capacitor; a carrier source outputting a plurality of carrier waves having a phase difference among said plurality of carrier waves; signal generator device outputting a signal as a function of characteristics of said plurality of carrier waves, whereby said apparatus provides conversion of DC power on said at least one DC line to AC power or conversion AC power on said AC circuit to DC power to thereby provide improved conversion efficiency by reduction in energy loss and a reduction in noise from the reactor.
 6. The apparatus according to claim 5, wherein said at least one DC lines includes two DC lines and said capacitor is connected between said two DC lines.
 7. The apparatus according to claim 5, wherein said at least one DC lines includes two DC lines and said capacitor is connected between said two DC lines.
 8. The apparatus according to claim 5 wherein said switching device is a Pulse Width Modulation converter.
 9. The apparatus according to claim 5 further including a plurality of signal wave generators respectively associated with each of said carrier waves.
 10. The apparatus according to claim 9, further including a plurality of comparators each of said comparators receiving a respective carrier wave and signal wave at its input and outputting an on or off signal to said switching device. 